选出正确的触发器描述
A、module D_FF ( input D,Clock,  output reg Q);  always@(Clock,D)    Q <= D;   
endmodule
B、module D_FF ( input D,Clock,  output reg Q);  always@(posedge Clock)    Q <= D;   
endmodule
C、module D_FF ( input D,Clock,  output reg Q);  always@(negedge Clock)    Q <= D;   
endmodule
D、module D_FF ( input D,Clock,  output reg Q);  always_ff@(posedge Clock)    Q <= D;   
endmodule
E、module D_FF ( input D,Clock,  output reg Q);  always_ff    Q <= D;   
endmodule