A. line timing
B. loop timing
C. internal timing
D. through timing
E. external timing
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Click the Exhibit button. A customer has several interconnected core rings (see exhibit). They want to create several irtual rings?utilizing their OC-192 backbone (nodes 1,2,3,4). What should you recommend?（）
A. PPMN with BLSR rings
B. PPMN with UPSR rings
C. 1:N protection on all core circuits
D. multi-ring interconnect with BLSR rings
A.10
B.32
C.64
D.84
E.96
Click the Exhibit button. Within an ONS 15454, you are provisioning a circuit on an unprotected UPSR ring. In the exhibit, which two must you configure?（） (Choose two.)
A. revertive
B. circuit type
C. circuit size
D. bidirectional
E. protected drops
F. switch on PDI-P
A.225 ft
B.450 ft
C.655 ft
D.900 ft
最新试题
Click the Exhibit button. What is the maximum allowable loss budget between the ONS 15216 Mux (left side) composite output and the ONS 15216 Demux (right side) composite input, with the optical values given in the exhibit? （）(Assume the worst case loss of 4.5 dB for 15216 200 GHz Mux/Demux and ignore power penalties or extra margin.)
What is the phenomenon called where different wavelengths of light travel at different speeds?（）
In the OSNR model for EDFA amplifiers, SNR OUT = 1/(1/SNR IN + FhvB/P IN ), what does SNR IN represent?（）
Click the Exhibit button. Given the following parameters: transmitter output (min): -2 dBm receiver input (min): -28 dBm 15216 Mux and Demux loss: 4.5 dB 16 channels maximum In which sites shown in the exhibit could the 15216 EDFAs be placed to minimize the number of EDFAs needed?（）
How is UPSR and BLSR traffic rerouted during a protection switch when a complete fiber cable cut occurs?（）
What protection method is used in 4F BLSR networks?（）
What are three factors that limit the maximum distance of an amplified optical signal without regeneration? （）(Choose three.)
If node 2 is accepting line timing from node 1, node 2 will send （）to node 1 as its SSM message.
If the power is 0 dBm, what is the power in mW?（）
SONET Path Terminating Equipment (PTE) requires which three line codes to be supported for DS1 and DS3 circuits?（） (Choose three.)